Logic devices are reaching increasingly faster speeds. As the speed continues to increase testing the devices becomes more difficult. This presents a problem.
Testers that are capable of dealing with source synchronous (sync) testing are expensive. This presents a problem.
Trying to guarantee source sync timing parameters by design (or characterization) is not a good solution because without actual testing one cannot be sure that a product meets the required specifications. Random defects and other anomalies may affect device performance. This may present a problem.
FIG. 3 illustrates a situation 300 with clocks and outputs in perfect alignment. Here a clock (CLK) 302 and data d0, . . . , dn (312-0, . . . , 312-n respectively) are all clocked by an internal clock (Int Clk) 320 into respective registers 304, 314-0, . . . , 314-n, then buffered respectively by 306, 316-0, . . . , 316-n, and presented as an output clock 308, and output data 318-0, . . . , 318-n all perfectly aligned at t0 322.
FIG. 4 illustrates a sync source datasheet specification (spec), for example, using the 250 MHz QDR (Quad Data Rate) SRAM as an example. One of the specs denoted as tCQHQX specifies that no output transitions will occur greater than 300 pS before the output clock. Likewise tCQHQV also specifies that no output transitions will occur greater than 300 pS after the output clock. FIG. 4 illustrates this situation 400 with clocks and outputs. Here a clock (CLK) 402 and data d0, . . . , dn (412-0, . . . , 412-n respectively) are all clocked by an internal clock (Int Clk) 420 into respective registers 404, 414-0, . . . , 414-n, then buffered respectively by 406, 416-0, . . . , 416-n, and presented as clock output 408, and data outputs 418-0, . . . , 418-n where for illustration purposes, output clock 408 is centered at t0 422, and output d0 418-0 illustrates an early output at tb 421 with respect to output clock 408 at t0, and output dn 418-n illustrates a late output at ta 423 with respect to output clock 408 at t0. The 250 MHz QDR spec requires these data out transitions to be within 300 ps of the output clock. How to test for this may present a problem.